1. Field of the Invention
The present invention concerns the design of flip-chip integrated circuits (ICs), and particularly relates to hexagonal arrangements of bump pads in a flip-chip IC.
2. Description of the Related Art
In recent years, manufacture of flip-chip integrated circuits (ICs) has become common. One example of a flip-chip configuration is shown in FIG. 1, which shows a cross-sectional view of a flip-chip 100. Referring to FIG. 1, flip-chip 100 includes a number of layers separated from each other by electrically insulating (typically oxide) layers 105. The transistors, resistors and other electronic devices, as well as some of the electrical connections between such electronic devices, are formed on semiconductor (typically polysilicon) layer 102. However, metal layers 104a to 104d are used for providing the bulk of the electrical connections between the electronic devices formed on semiconductor substrate 102. By providing such metal layers, valuable space on the semiconductor layer can be conserved for forming electronic devices.
Flip-chip 100 also includes a top layer 106, on which are formed multiple solder bump terminals 108, called bump pads, which are used as the input/output terminals for die 100. For mounting purposes, flip-chip die 100 is "flipped" so that top layer 106 faces downward. Top layer 106 then is bonded to a substrate which may be a passive carrier, such as a printed circuit board, or may be another semiconductor chip. Specifically, each bump pad 108 typically is solder bonded to a corresponding pad on the substrate, thereby forming the required electrical connections. The substrate then is usually bonded directly to a printed circuit board, on which additional flip-chips and/or ICs utilizing other types of packaging are mounted.
Flip-chip integrated circuits ordinarily are designed in a multi-phase process. The physical design phase of the design process involves deriving information for fabricating the integrated circuit, based on an input circuit description called a netlist. Two of the most difficult problems in physical design are layout and routing. Layout is the step of locating a physical position on the surface of the semiconductor layer for each of the electronic components specified in the netlist. Routing is the step of mapping out electrically conductive traces, or wires, between the electronic components, also according to the netlist. These two problems are interrelated in that a good layout often will greatly simplify the routing step and a poor layout may render routing unfeasible. Because a typical IC can contain hundreds of thousands or millions of electronic components, a designer usually relies heavily on computer-aided design tools to perform layout and routing.
Frequently, flip-chips such as flipchip 100 utilize rectangular-based layout and routing. An example of a particular rectangular-based layout is illustrated in FIG. 2 which provides a representational illustration of die 100. The logic circuitry of integrated circuit 100 is formed in the interior portion 120 of the semiconductor layer 102, while the periphery of semiconductor layer 102 is used for the I/O devices 116. The logic portion 120 includes a number of functional circuit blocks, which can have different sizes and shapes and which are laid out based on a rectangular grid. The larger blocks include central processing unit (CPU) 121, read-only memory (ROM) 122, clock/timing unit 123, random access memories (RAMs) 124, and I/O unit 125 for providing an interface between CPU 121 and various peripheral devices. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries. The logic portion also includes tens of thousands, hundreds of thousands or even millions or additional small cells 126. Each cell 126 represents either a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
All of the small cells 126 and macroblocks 121-125 shown in FIG. 2 are laid out on semiconductor substrate 102 according to a fixed rectangular grid pattern. That is, each cell 126 occupies a single grid slot and each of macroblocks 121-125 occupies an integral number of grid slots. However, it should be noted that many conventional rectangular-based techniques, and rectangular-grid-based techniques in particular, permit deviations from the rectangular grid pattern in certain cases, such as for non-standard sized cells.
Another example of a conventional rectangular-based layout is illustrated in FIG. 3. The layout of FIG. 3 often is preferable when, because many non-standard-sized cells are to be used, it would be impractical to align the cells in both x and y coordinates using grid-based layout. This approach therefore utilizes multiple cell columns 140, each including a column of cells 145, each cell having a standard width but potentially different lengths. Thus, while in the grid-based layout approach cells generally are aligned with certain established (x,y) coordinates, in the cell-column approach generally are aligned only with respect to the x coordinate. Similar to rectangular-grid-based placement, the cell-column approach also permits occasional deviations from a strict rectangular layout. For instance, larger cells or macroblocks, such as macroblock 147, may span more than a single cell column.
For each cell column 140, one of the metal layers, typically the first metal layer, includes a power rail 141 and a ground rail 142. The cells 145 connect to the power rail 141 and ground rail 142 using interlayer connections called vias. In the example shown in FIG. 3, macroblock 147 is provided with an external power ring 148 and external ground ring 149 for routing power rails 141 and ground rails 142 around the macroblock.
In either of the foregoing techniques, wire routing between the cells also is rectangular-based, i.e., primarily utilizes horizontal and vertical trace extensions. As noted above, most of the wire routing is done in the IC's metal layers. An example of such rectangular-based routing is illustrated in FIG. 4. One typical wire connection in FIG. 4 is wire 170, which is routed between cell 160 and cell 162. Wire 170 includes horizontal portion 170a, vertical portion 170b and horizontal portion 170c. Similarly, each of the other wires shown in FIG. 4 interconnecting the cells 160-166 includes only vertical and horizontal segments. However, similar to rectangular-based layout, in certain cases wire traces which are not purely horizontal or purely vertical sometimes are used in rectangular-based routing.
Rectangular-based layout and routing provides a structured framework in which to approach the physical design problem. This is particularly important when using automated software tools, which function according to a fixed set of pre-defined rules. For example, in rectangular-based layout the CAD layout tool can simply leave channels between columns or rows of cells based on anticipated routing needs. An advantage of using rectangular-based routing is that such a technique often is relatively easy to implement in a manner which avoids unwanted wire crossings.
In this latter regard, rectangular-based routing frequently is implemented by routing the majority of the vertical wire segments in one metal layer (such as metal layer 1) and the majority of the horizontal wire segments in a different metal layer (such as metal layer 2). This is illustrated in FIGS. 5A and 5B. In particular, FIG. 5A illustrates metal layer 1 on which the vertical wire segments shown in FIG. 4 are routed and FIG. 5B illustrates metal layer 2 on which the horizontal wire segments shown in FIG. 4 are routed. The horizontal and vertical segments for a particular wire are connected to each other using via 175. Similarly, connections between wires on the metal layers and the cells on the semiconductor layer are made using vias. In certain specific cases, exceptions are sometimes made and vertical segments are routed on a horizontal metal layer or horizontal segments are routed on a vertical metal layer. However, by routing mainly horizontal segments on one layer and mainly vertical segments on a different layer, the risk of an inadvertent wire crossing, or conversely, the planning required to avoid such a wire crossing, is usually minimized.
Thus, rectangular-based placement and routing often can greatly simplify the physical design process. As noted above, this is particularly important because many flip-chip integrated circuits contain hundreds of thousands or millions of cells which must be laid out, and for which interconnecting wires must be routed.
In correspondence with component layout and wire routing, in the conventional flip-chip design, layout of bump pads 108 also is rectangular-based. Specifically, in conventional layout bump pads are usually arranged in a rectangular array. FIG. 6 illustrates a conventional rectangular array of bump pads 108. In particular, FIG. 6 shows a certain bump pad 108a and its nearest neighbors 108b through 108e. Connecting the midpoint of each bump pad 108 to its nearest neighbors in the conventional rectangular-based arrangement results in a pattern of non-overlapping rectangles 190. The conventional bump pad arrangement depicted in FIG. 6 therefore is referred to herein as a rectangular array. Ordinarily, the center-to-center distances between bump pad and its nearest neighbors are fixed at a constant value based on fabrication requirements. Accordingly, each of the rectangles 190 typically is square.
It is noted that in actual implementation some of the positions indicated in FIG. 6 as containing a bump pad actually are left open. This frequently is the case, for example, with bump pad positions near the center of the die. Sometimes it is difficult to route wires from certain of these bump pad positions to the outer edges of the die, and therefore they are left empty, in a process known as de-populating.
An advantage of flip-chip integrated circuits over wire bond ICs is the ability of flip-chips to provide more pads for inputting and outputting external signals. In particular, with flip-chip ICs pads can be implemented across the entire surface of the die, rather than solely at the die's periphery. As technology advances even further, however, the demand continues to increase for even more bump pads than can be provided by conventional flip-chip techniques.